This invention relates to an instruction parallel issue and execution administrating device for use in a processor of a superscalar type in administrating parallel issue and execution of a predetermined number of instructions in parallel.
It is known and widely used on putting a general purpose processor, particularly a microprocessor, at a high performance to use a superscalar technique. In the manner described by Mike Johnson in his book entitled "Superscalar Microprocessor Design" published by Prentice Hall, in particular, Chapter 3, pages 31 to 55, a processor is operable according to the superscalar technique as follows. A predetermined peak number of instructions are concurrently fetched in parallel and decoded into a plurality of decoded instructions. From these decoded instructions, a simultaneously executable number of instructions are dynamically identified as a plurality of identified instructions. The identified instructions are issued in parallel to a plurality of arithmetic-logic and memory access units for parallel execution. In this manner, a superscalar processor deals with parallel processing of the instructions.
A conventional superscalar processor comprises for the parallel processing an instruction parallel issue administrating device and an instruction parallel execution administrating device. In general, the instruction parallel issue administrating device is called a reservation station. The instruction parallel execution administrating device is referred to as a recorder buffer.
In the manner which will later be described in greater detail, the instruction parallel issue and the instruction parallel execution administrating devices are operable as follows. The instruction parallel issue administrating device temporarily stores the decoded instructions as stored instructions, typically eight in number. Tests are carried out whether or not each stored instruction can be issued as an issued instruction. If present, at least one issued instruction is issued. If found impossible to issue as such issued instructions from time to time, a stored instruction is held in the instruction parallel issue administrating device as a preissued instruction. In a next processing cycle, a test is carried out whether or not the preissued instruction can now be issued.
On judging whether or not each stored instruction can be issued, it is tested whether or not all operands are already produced for use by the stored instruction under consideration. It will herein be presumed that such requested or required operands are two in number for each instruction.
The instruction parallel execution administrating device temporarily stores a plurality of preconfirmed results of execution of the issued instructions as stored results, typically sixteen in number. This temporary storage is in order to insure an execution order or sequence in which the issued instructions are actually executed and which may be different from a fetch and decode order of simultaneously fetching and decoding the predetermined peak number of instructions from time to time. The preconfirmed results are so called because such results are produced by the issued instructions, the execution of which is not yet finally confirmed. The stored results are produced for use as the operands of each issued instruction.
In connection with the foregoing, the simultaneously executed number is either equal to or approximately equal to the predetermined peak number and is the number of instructions which are actually executed in parallel to their ends. It will be assumed that the predetermined peak number is equal to three and that the simultaneously executed number is equal also to three. In this event, the instruction parallel issue administrating device must comprise forty-eight comparators. The instruction parallel execution administrating device must comprise 144 comparators.
When each of the predetermined peak number and the simultaneously executed number is equal to nine, the comparators must be included in the instruction parallel issue administrating device as many as 432 and in the instruction parallel execution administrating device as many as 1,296 and thus 1,728 in total. In this manner, the number of comparators increases nearly in proportion to a square of the number of instructions which should be issued, executed, and executed to their ends.
Inasmuch as this great number of comparators must individually be controlled, each of the instruction parallel issue and the instruction parallel execution administrating devices has been complicated in circuit structure. Moreover, each of the devices has had an objectionably great circuit scale. Simultaneous and parallel comparison by these comparators has made it unavoidable to consume a great amount of electric power. On increasing a degree of parallel processing, it has been inevitable to allow a delay in the parallel processing. Although such a conventional superscalar processor has been actually manufactured and practically used for parallel issue and parallel completion of execution of three instructions, it has been difficult to develop a superscalar processor of a highly raised architecture capable of concurrently executing an increased number of instructions in parallel, such as ten instructions.